Senior SOC Physical Design Engineer - System on Chip (SoC) Development & Tapeout

PERSOL is seeking a highly skilled and experienced Senior SOC Physical Design Engineer to join our team in Badung, Bali. In this role, you will be responsible for the physical design of System on Chip (SoC) development and tapeout, ensuring the successful implementation of complex integrated circuits.

As a Senior SOC Physical Design Engineer, you will work closely with cross-functional teams to deliver high-performance, low-power SoC designs that meet customer requirements and industry standards.

If you are passionate about SoC development and have a proven track record in physical design, we encourage you to apply for this exciting opportunity.

📋 Tanggung Jawab Pekerjaan

Tanggung Jawab:

• Lead the physical design process for SoC development, including floorplanning, placement, clock tree synthesis, and routing.
• Ensure the physical implementation of SoC designs meets timing, power, and area constraints.
• Collaborate with design and verification teams to resolve design issues and optimize the physical design.
• Perform static timing analysis (STA) and power analysis to verify the design's performance and power consumption.
• Develop and maintain physical design methodologies and best practices.
• Mentor junior engineers and contribute to the professional development of the team.
• Stay up-to-date with the latest advancements in SoC design and physical design tools.
• Participate in tapeout activities, including design sign-off, GDSII generation, and tapeout preparation.

🎓 Kualifikasi & Syarat

Kualifikasi:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 8 years of experience in SOC physical design, with a focus on advanced nodes (e.g., 7nm, 5nm, or below).
• Strong knowledge of physical design tools, such as Cadence Innovus, Synopsys IC Compiler, or similar.
• Experience with static timing analysis (STA) and power analysis tools, such as Synopsys PrimeTime or Cadence Tempus.
• Proven track record of successful SoC tapeouts and experience working with foundry design kits.
• Excellent problem-solving skills and the ability to work in a fast-paced, collaborative environment.
• Strong communication skills, both written and verbal, with the ability to present technical information to non-technical stakeholders.
• Fluency in English is required, both written and spoken.

🛠️ Keahlian

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